1. Field of the Invention
The present invention relates to a photoelectric conversion device in which plural pixel columns, in which plural pixels are arrayed, are arranged and an independent readout wiring is individually provided for each pixel. The invention also relates to a multichip module type image sensor, a contact image sensor, and an image scanner on which the plural photoelectric conversion devices are mounted.
2. Related Background Art
Recently, in an information processing field, in contrast to the conventional scaling-system line sensor in which an optical system is used, the same-magnification system contact image sensor on which plural image sensor chips are multichip-mounted is actively developed as the line image scanner.
For example, Japanese Patent Application Laid-Open No. H11-234472 discloses a structure of the contact image sensor in which the image sensor chips having one-line light receiving element arrays are multichip-mounted. FIG. 6 is an equivalent circuit diagram showing a color image sensor in which a three-line light receiving element array is formed by the image sensor chips having one-line light receiving element arrays disclosed in Japanese Patent Application Laid-Open No. H11-234472.
Referring to FIG. 6, image sensor chips 1 and 1′ which are of the photoelectric conversion device are multi-mounted, and a clock CLK for driving each image sensor chip and a start pulse SP are input to each image sensor chip. The image sensor chips 1 and 1′ include N-bit delay means (N-bit pre-shift register) 2 and 2′, readout circuit blocks 3 and 3′ including K-by-3-bit shift registers 11 and 11′, K-bit-by-3-column light receiving element arrays (three pixel columns) 4 and 4′, timing generation circuits 5 and 5′, and signal output amplifiers 6 and 6′.
The signals, located N bits (K-N bits) ahead when the readout of the bits of each image sensor chip is ended, are output from the portions located N bits ahead from the final register of the shift registers 11 and 11′ as the start signal of the next chip in next chip start signals SD and SD′.
The timing generation circuits 5 and 5′ driven by the clock signal CLK and the start pulse signal SP generate pulses for driving the light receiving element arrays 4 and 4′ and pulses φ1 and φ2 for driving the shift register 11 and 11′. The pulse φ1 is output to drive lines 7 and 7′, and the pulse φ2 is output to drive lines 8 and 8′. The reason why the start pulse signal SP is commonly output to the image sensor chips is that the operation start of each image sensor chip is synchronized.
Each of the signal output amplifiers 6 and 6′ amplifies an image signal, which is read out onto one signal output line through a switch turned on and off by each sift signal of the shift registers 11 and 11′. The amplified image signals are output as signals Vout by controls signals of the timing generation circuits 5 and 5′. The signal output amplifiers 6 and 6′ includes constant current circuits therein. The constant current circuits start supply of power source at the same time when the start signal is input, and the constant current circuits enables a normal amplifying operation to be performed when the N-bit clock signals are input from the start signal.
FIG. 7 is a timing chart showing the drive pulses φ1 and φ2 of the shift register 11 for the clock signal CLK.
FIG. 7 is the timing chart when the delay means 2 shown in FIG. 6 is set at four bits. Therefore, the shift registers 11 and 11′ start the first shift register operation while delayed by four bits from the start pulse signal SP.
As shown in FIG. 7, the drive pulses φ1 of the shift registers 11 and 11′ are synchronized with a high level of the clock signal CLK, and the drive pulses φ2 are synchronized with a low level of the clock signal CLK. The signal output Vout is taken out in synchronization with the drive pulses φ1 and φ2. Therefore, when the first bit of the shift register 11 corresponds to the drive pulse φ1, odd-number bits are the signal output synchronized with the drive pulse φ1, and even-number bits are the signal output synchronized with the drive pulse φ2.
In FIG. 7, the reference sign SA denotes a signal output of the image sensor chip 1, and the reference sign SC denotes a signal output of the image sensor chip 1′. Therefore, the whole signal output Vout is obtained as shown in FIG. 7. Each image sensor chip outputs the signal, located four bits ahead from the final bit, as the start signal SB of the next image sensor chip.
Thus, a large-size original can directly be read as the multichip module type image sensor, and a read rest time between the chips and a difference in signal output level can be eliminated.
FIG. 8 is an equivalent circuit diagram showing the readout circuit block 3 and light receiving element 4 (only two-pixel-by-three-column light receiving element is shown) shown in FIG. 6. Light receiving elements (constituting the pixel) r1 to b2 include photodiodes PDr1 to PDb2 which are of the photoelectric conversion element. For example, red (RED), green (GREEN), and blue (BLUE) color filters are arranged on each photodiode column.
The readout circuit block 3 includes readout switches M1b1, M1r1, . . . , and M1g2, signal transfer switches M2b1, M2r1, . . . , and M2g2, MOS source follower input transistors M3b1, M3r1, . . . , and M3g2, MOS source follower constant current loads CSb1, CSr1, . . . , and CSg2, reset switches M4b1, M4r1, and M4g2 which are of means for resetting the photodiodes PDr1 to PDb2, storage capacitances CAPb1, CAPr1, . . . , and CAPg2 in which capacitances are temporarily stored, a shift register 11, a common output line 14, and a common output line reset switch 15. The light receiving elements r1 to b2 and the readout circuit block 3 are connected with readout wirings 16b1, 16r1, . . . , and 16g2.
Photocarriers generated by the photoelectric conversion in the photodiodes PDr1 to PDb2 of the light receiving elements r1 to b2 shown in FIG. 8 are transmitted to MOS source follower input transistors through the readout wirings, and charge-voltage conversion is performed to the photocarriers. Then, the signal transfer pulse φT is changed to the high level to turn on all the signal transfer switches M2b1, M2r1, . . . , and M2g2, and the light signals are collectively transferred to the storage capacitances CAPb1, CAPr1, . . . , and CAPg2 in all the pixels. Then, the readout switches M1b1, M1r1, . . . , and Mlg2 are sequentially turned on by the readout pulses φSR1 to φSR6 sequentially turned to the high level from the shift register 11, and signal voltage is read out onto the common output line 14 while the capacitance is divided.
FIG. 9 is a schematic plan view showing the light receiving element 4 shown in FIG. 8. In FIG. 9, the signs RED, GREEN, and BLUE designate the red, green, and blue color filters formed on the photodiodes PDr1 to PDb2. A material such as dye or pigment is usually used for the color filter. The readout wirings 16r1 to 16b2 from PDs (hereinafter, each photodiode of the photodiodes PDr1 to PDb2 is referred to as PD) run between PDs to the readout circuit block 3 in order to obstruct incident light.
After the signals of the photodiodes PDr1 to PDb2 are collectively transferred to the storage capacitances CAPb1, CAPr1, . . . , and CAPg2, the signals are read out through the signal output amplifier 6 in the order of the signals corresponding to PDb1, PDr1, PDg1, PDb2, PDr2, and PDg2.
However, the following problems are generated when the pixels are arranged as shown in FIG. 9. Lengths of the readout wirings 16 connecting the photodiodes PD and the input transistors M3 differs from one another by at least a pixel pitch in the pixel columns (light receiving element arrays), which creates a difference in wiring capacitance associated with the readout wiring 16. The photocarrier generated by the photoelectric conversion in the photodiode PD is converted into the signal voltage by the capacitance associated with the photodiode PD. When the pixel columns differ from one another in the wiring capacitance of the readout wiring 16, there is the problem that a difference in sensitivity is generated in each pixel column. The total capacitance associated with the photodiode PD is increased by providing the readout wiring 16 to the readout circuit block 3, which results in the problem that the sensitivity is decreased.
As described with reference to FIG. 8, the following problems are generated when the signals from the pixel columns are read out at the same timing. As shown in FIG. 9, the readout wirings 16 connecting the photodiodes PD and the MOS source follower input transistors M3 are provided from the pixel columns to the readout circuit block 3 respectively. Therefore, a crosstalk is generated by a parasitic capacitance between the readout wirings 16 (for example, between the readout wiring 16g1 and 16b2), which leads to color mixture to generate the problem that image quality is remarkably decreased in the color image. This is the new problem which is not generated in the case of an area sensor. In the area sensor, a vertical shift register is provided in addition to a horizontal shift register corresponding to the shift register 11, and the signal is read out onto the common readout wiring (vertical signal line) provided in each pixel column by the vertical shift register while readout timing is changed. Accordingly, even if the readout wiring are arranged adjacent to each other like the readout wirings 16g1 and 16b2 of FIG. 9, because the pixel columns differ from each other, the signals are not simultaneously read out in the readout wirings 16g1 and 16b2, which generates no problem. However, in the case of the multichip module type image sensor, the vertical shift register cannot be arranged because the pixel column is arranged to an edge portion of the chip. Therefore, it is difficult to avoid the above problem.
The crosstalk problem is not limited to the sensor on which the color filter is mounted. Even in the mono-chrome image sensor chip and mono-chrome multichip module type image sensor on which the color filter is not mounted, sometimes the signals from the plural pixel columns (plural light receiving element arrays) are read out at the same time. Accordingly, when the wirings are arranged adjacent to each other, there is generated the problem that the generation of the crosstalk worsens image contrast.